The invention relates generally to generation of VPP and WLL voltages for a DRAM array and, more particularly, to generation of such voltages for use with a lower-than-nominal array threshold voltage.
In conventional DRAM arrays, information is stored in a given DRAM cell by driving a wordline WL appropriately to activate a transfer transistor (whose gate is connected to the wordline) and thereby transfer charge into the cell capacitor. In general, the retention time of the cell, and thus the performance thereof, increases with the amount of charge transferred to the cell. The transfer transistor of a given cell is activated for transferring charge into the cell by application of a voltage VPP to the wordline, and the transfer transistor is switched off by application of a voltage WLL (wordline low) to the wordline. This is illustrated generally in FIG. 1.
In order to transfer the maximum possible charge to the cell, a large VPP must be applied to the gate of the transfer transistor via wordline WL. More specifically, VPP must be much greater than the threshold voltage Vt of the transfer transistor. Due to performance (i.e., speed) requirements, the time available to transfer the charge into the cell is limited, and is typically reduced with each new generation of DRAM arrays. Increases in the VPP voltage permit reductions in the charge transfer time. However, due to reliability concerns, the maximum VPP is limited due to the maximum allowable electric field across the gate oxide of the transfer transistor.
Due to normal process variations, the threshold voltage Vt of the transfer transistor can be higher than the nominal threshold voltage VtNOM, which reduces the voltage difference VPPxe2x88x92Vt (also referred to as the overdrive), thereby reducing the charge transfer to the cell. This disadvantageously impacts the cell""s retention capability and thus the product yield.
Conventional DRAM array chips include VPP tracking circuits that basically measure the threshold voltage Vt of one (or several) transfer transistors, and then increase the VPP voltage, if required, to maintain a desired overdrive (VPPxe2x88x92Vt), thereby insuring that the maximum charge is always transferred to the cell. Although such VPP tracking can be used to compensate for a higher-than-normal Vt, nevertheless the maximum value of VPP is limited by the aforementioned gate oxide reliability considerations. In fact, due to the thinner gate oxides used in the latest DRAM technologies, the nominal VPP value is approaching the reliability limit of the gate oxide, so the aforementioned VPP tracking is no longer a viable option because the VPP voltage typically cannot be increased beyond its nominal value.
When a DRAM array has a lower-than-nominal threshold voltage, the WLL voltage may not completely shut off the transfer transistor, in which case the charge can leak out of the cell capacitor, thereby disadvantageously reducing the cell retention time and disadvantageously impacting the product yield. Conventional DRAMs typically use a grounded WL scheme, wherein the WLL voltage is fixed and cannot be lowered below 0V. Thus, with the grounded WL scheme, a lower-than-nominal threshold voltage cannot be compensated for by reducing the WLL voltage.
It is therefore desirable to provide compensation for lower-than-nominal threshold voltage in a DRAM array, thereby improving the cell retention time and the product yield.
The present invention utilizes a negative wordline low (NWLL) scheme that permits lowering WLL to compensate for a lower-than-nominal threshold voltage. Further according to the invention, VPP is tracked together with WLL in order to maintain a generally constant voltage swing therebetween, thereby advantageously avoiding damage to the gate oxides in the wordline driver circuits. After determining a desired overdrive voltage (VPPxe2x88x92Vt) and a desired voltage swing between VPP and WLL, VPP can be tracked with the lower-than-nominal threshold voltage to maintain the desired overdrive voltage, and WLL can be tracked with VPP to maintain the desired voltage swing between VPP and WLL.